1. Field of the Invention
The present invention relates to a method for forming CMOS circuits and, more particularly, to a method for forming mixed-signal CMOS circuits that include electrically-erasable non-volatile memory cells.
2. Description of the Related Art
Historically, the integration of electrically-erasable non-volatile memory cells into mixed-signal CMOS circuits (analog and digital circuits) has been hampered by the higher voltage requirements of the memory cells. The higher voltage requirements, in turn, require increased isolation, thicker gate oxide, deeper junctions, and additional voltage sources that substantially increase the device size and the process complexity required to make an integrated device.
For example, current CMOS logic devices utilize minimal isolation and shallow junction depths, and operate on approximately 3.3 volts. Analog devices have similar isolation and junction depth requirements, but typically operate on 5.0 volts to obtain a wider dynamic range.
On the other hand, conventional electrically-erasable non-volatile memory cells, such as floating-gate tunneling oxide (FLOTOX) EEPROM and FLASH EPROM cells, utilize significantly more isolation and deeper junction depths, and typically require 12-15volts to program and erase the cells.
Recently, however, low-voltage FLASH EPROM cells based on one and two transistor configurations have been described in U.S. Pat. Nos. 5,477,485 and 5,511,021, and U.S. patent application Ser. Nos. 08/422,146 and 08/654,103. These transistor configurations require significantly less isolation, shallower junction depths, and lower operational voltages.
As a result, there is a need for a method for fabricating mixed-signal CMOS circuits that include these transistor configurations.